1. Field of the Invention
The present invention generally relates to an error detecting and correcting system, and more particularly to an error correction apparatus which detects and corrects read errors while reproducing digital data that have been encoded with Error Correcting Codes (ECC) and recorded on a magnetic tape using a rotary head.
2. Description of the Related Art
The so-called data recorders which record digital data on magnetic tapes have been used as external memories for computers. A data recorder scans a magnetic tape with a magnetic head provided on a rotary drum to record and reproduce data on and from the tape. A defective tape, a magnetic head clogged with dirt or dust, and the like may, however, prevent correct data reproduction by the magnetic head. This phenomenon is termed "drop-out". Reproduced signals may be transformed to indicate different values due to noise. In data reproduction, therefore, there is a constant risk that data may not be correct.
In order to prevent the production of such incorrect data, a method of encoding data to be recorded with ECC is employed. In the encoding with ECC, data called parity digits are appended to the data to be processed for error correction. A data recorder executes the error detection and correction defined by ECC, based on the parity digits, to correct errors included in the reproduced data.
The number of errors correctable by ECC (error correction capability), however, is limited depending on the number of parity digits in use. When there are a number of errors, therefore, all the errors may not be completely corrected by the error correction. Such incomplete error correction can fall under two types. The first one is that although the existence of errors can be detected, the correction of the data is impossible. The second is that those data including errors are erroneously outputted as correct data.
The first type of problem can be solved as follows. When the existence of errors has been detected and yet the data are uncorrectable, the error correction apparatus performs again reproducing operation. That is, the tape is rewound by a certain amount to allow reread of the data read out just before, and decoding is repeated. This operation is referred to as "read retry". The retry may sometimes makes it possible to read data correctly, for example, relieving the head or tape of the clogging or dirt. To avoid the suspension of processing caused by retrying unlimitedly, an upper limit is generally set for the retry number. When the upper limit is exceeded, determination is made that data reading of a part concerned is impossible. As a result, at least the output of incorrect data can be prevented.
The second type of incomplete error correction is further divided into two types. Those two types involve so-called miscorrection and misdetection. The miscorrection represents a case where errors, when there are many, are erroneously located and data requiring no correction at all are corrected. The misdetection represents a case where a value of data including a number of errors happen to be altered to a different allowed value, resulting in an erroneous determination in the parity check that the data are correct. The error correction with ECC inevitably involves miscorrection and misdetection at a certain rate.
The probability of the miscorrection and misdetection, which depends on the structure of each ECC, is very small. In case of an isolated error, for example, the probability represents a value as small as once or none at all for tens or hundreds of years. The miscorrection and misdetection will offer, therefore, little problem in reproducing equipments other than the data recorders, such as an apparatus for reproducing music.
In reproducing data recorded on a magnetic tape, however, the above-described drop-out or the like may locally increase the error rate. In such a case, the probability of the miscorrection and misdetection is considerably increased. If the miscorrection and misdetection is overlooked in the data recorders, erroneous data are externally outputted as correct values. The data recorders record data of a low redundancy, unlike music or the like. If erroneous data are outputted, therefore, they may cause a significant failure in the data processing performed, for example, in a host computer coupled thereto. Consequently, the probability of the misdetection and miscorrection has to be made as small as possible in data recorders.
One method of solving the above-mentioned problem is to encode and decode data using an ECC of a high error correction capability. This ensures a substantial reduction in the probability of the miscorrection and misdetection.
However, the above-mentioned method has the following disadvantages. To enhance the error correction capability, it is required to improve the redundancy of data by increasing the number of parity digits used with the ECC. It is generally known that when the number of parity digits is increased, hardware for data encoding and decoding gets rapidly complicated. In this method, therefore, the economical requirements for obtaining highly reliable data with a lower cost can not be met.
Another method is to perform multi-encoding and multi-decoding with a plurality of ECC systems independent of each other each of which does not have enough error correction capability by itself. In this method, for example, data to be recorded are divided into a plurality of units. Each unit data contains a plurality of words each comprising a plurality of bits. The words are arranged, for example, two-dimensionally, or logically to form rows and columns. The words contained in each unit are doubly encoded and decoded in both directions of the rows and the columns. As an example of such a method, "Doubly Encoded Read Solomon Code" has been widely used.
Processing with such multi-encoded ECCs can bring about the following advantages.
(1) Each ECC employs a relatively small number of parity digits. The excessive complication of the hardware for error correction, therefore, can be avoided.
(2) Each ECC has a low error correction capability. By employing a plurality of ECC systems and thus performing error correction processing along the systems different from and independent of each other, however, the entire error correction capability is sufficiently enhanced.
Referring to FIG. 1, a conventional error correction apparatus includes: a demodulation circuit 12 for demodulating data that have been multi-encoded with error correcting codes and modulated and recorded on tracks T1 and T2 of a magnetic tape 10; a buffer memory 14 for storing output of the demodulation circuit 12; an error correction circuit 62 for multi-decoding with the ECCs the data stored in the buffer memory 14, and for, at the end of the multi-decoding, outputting an error flag signal 64 indicative of whether correction has been possible or not; and a controller 20a for receiving output of the error correction circuit 62, for determining whether retry is necessary or not, and for controlling the demodulation circuit 12, the buffer memory 14 and the error correction circuit 62 to repeat the processings if retry is necessary and to proceed to subsequent data processings if not necessary.
The signals recorded on the magnetic tape are divided into a plurality of frames each including the two tracks T1 and T2. The demodulation circuit 12 reads data of one frame and outpours the read-out data to the buffer memory 14.
The controller 20a includes a retry counter 58 for counting the number of retries made for one error correction processing, a memory 60 for storing an upper limit of the retry number in advance, and a retry determining circuit 66 for determining as to whether retry should be made or not according to values of the error flag 64, the retry counter 58 and the memory 60.
The error correction apparatus further includes an interface 16 connected to output of the buffer memory 14 for outputting contents stored in the buffer memory 14, for example, to a host computer.
The controller 20a includes, for example, a microcomputer and the like. FIG. 2 is a schematic flow chart of a program executed in the controller 20a for retry control.
Referring to FIGS. 1 and 2, a conventional error correction apparatus operates as follows. The tape 10 is driven by a capstan motor, a capstan, a pinch roller and the like, which are not shown, and guided by an unshown tape guide or the like to run in a predetermined direction.
The demodulation circuit 12 reads data recorded on the tracts T1 and T2 using an unshown rotary head, performs required processings such as equalization and demodulation, and applies the processed data to the buffer memory 14.
The buffer memory 14 stores one-frame data received from the demodulation circuit 12 (step S101).
The error correction circuit 62 initially makes the retry counter 58 represent zero by its content A (step S102). The circuit 62 decodes with the ECCs data stored in the memory cell 14 sequentially from the lowest level, and corrects errors if any contained therein (step S103). When the error correction processing for the lowest level is completed, another error correction processing is performed for the subsequent level. Even if an uncorrectable error has been detected at a lower level, the error may disappear in another error correction processing for a higher level. When the error correction processing is completed up to the highest level, the error correction circuit 62 makes determination whether or not an uncorrectable error has been detected or not (step S104).
If such an error has been detected, the error correction circuit 62 makes the error flag signal 64 logical high. If such an error has not been detected, or it is determined that complete error correction has been made, the error correction circuit 62 makes the error flag signal 64 logical low.
The retry determining circuit 66 operates as follows, depending on value of the error flag signal 64. When the error flag signal 64 is logical low, the retry determining circuit 66 resets the retry counter 58. The retry determining circuit 66 controls the buffer memory 14 and the interface 16 such that contents stored in the memory 14 are transmitted through the interface 16 to a host computer (step S106). The retry determining circuit 66 further controls the demodulation circuit 12 and the memory 14 such that data recorded on the subsequent tracks T1 and T2 of the tape 10 are read out and the subsequent error correction processing begins.
When the error flag signal 64 is logical high, the retry determining circuit 66 compares the content A of the retry counter 58 with a maximum retry number L stored in the memory 60 (step S107). If the number A represented by the retry counter 58 is smaller than the maximum retry number L, the retry determining circuit 66 adds one to the value A of the retry counter 58 (step S109). The retry determining circuit 66 controls the demodulation circuit 12 and the memory 14 such that data read out just before is reread (step S110). The retry determining circuit 66 further control the error correction circuit 62 to perform error correction processing in due order from the lowest level to the highest level (step S103).
If the value A of the retry counter 58 is not smaller than the maximum retry number L, the retry determining circuit 66 externally outputs a message of "DATA-ERROR". The retry determining circuit 66 then abandons the processing (step S108). Thus, if the detection of errors does not disappear in spite of the retries of the maximum retry number, the processing is abandoned. Accordingly, erroneous data is never externally outputted.
As described above, when data is multi-encoded with ECCs, errors contained in the data can be corrected with a relatively simple hardware but with a large capability.
However, the conventional apparatus has the following problems. The conventional apparatus has high error correction capability due to the multi-encoded ECCs employed therein. It is true that the probability of miscorrection and misdetection taking place in the conventional apparatus is low, but there is no denying that it takes a certain value.
For example, when a miscorrection or the like is made in the error correction processing at a certain level, the occurrence of the miscorrection or misdetection will be usually checked in the error correction processing at a higher level. However, also the probability of miscorrection or the like taking place in the error correction processing at the higher level is not null, though it may be extremely low. Especially when a miscorrection or the like occurs in the error correction processing at a higher level, there is not left much opportunity that the occurrence of the miscorrection or the like is checked. Thus, the probability that a miscorrection or the like in a higher-level processing will be detected is low. If retry is repeated many times, therefore, the probability become relatively high that the processing will terminate without detecting a occurrence of miscorrection or the like if the miscorrection occurs, for example, at a higher level.
As described above, the probability of a miscorrection or the like taking place should be made as small as possible. Meanwhile, the error correction capability of an error correction apparatus should not be reduced while the excessive complication of hardware therefor should be avoided.